The present invention relates to a SIMD (Single Instruction Multiple Data) type processor, and particularly to a SIMD type processor that handles three-dimensional vectors or quaternions.
A number referred to as a quaternion is used to perform object rotation, spherical interpolation, and the like in a three-dimensional graphics process. The quaternion is a three-dimensional vector added to a scalar value, and represents an axis in a three-dimensional space and rotation on the axis. A quaternion P is represented by a scalar value p and a three-dimensional vector U as follows.P=[p; U]
Setting p=Aw and U=(Ax, Ay, Az), and using imaginary units i, j, and k, the quaternion P is also represented as follows.P=Aw+Axi+Ayj+Azk 
The imaginary units i, j, and k have the following relations.ii=jj=kk=ijk =−1ij=kji=−k
Similarly, setting a quaternion Q as Q=[q; V], and setting q=Bw and V=(Bx, By, Bz),Q=Bw+Bxi+Byj+Bzk 
A quaternion product PQ of the quaternion P and the quaternion Q is obtained by
                                                        PQ              =                            ⁢                              (                                                      -                    AxBx                                    -                  AyBy                  -                  AzBz                  +                  AwBw                                )                                                                                                        +                                ⁢                                  (                                      AxBw                    +                    AyBz                    -                    AzBy                    +                    AwBx                                    )                                            ⁢              i                                                                                          +                                ⁢                                  (                                                            -                      AxBz                                        +                    AyBw                    +                    AzBx                    +                    AwBy                                    )                                            ⁢              j                                                                                          +                                ⁢                                  (                                      AxBy                    -                    AyBx                    +                    AzBw                    +                    AwBz                                    )                                            ⁢              k                                                                          =                            ⁢                              Mw                +                Mxi                +                Myj                +                Mzk                                                                        (                  Equation          ⁢                                          ⁢          1                )            
Sixteen multiplications and 12 additions and subtractions are required to obtain the components (Mw, Mx, My, and Mz) of such a quaternion product. When these operations are to be performed simultaneously, a necessary circuit scale may be increased.
When the two quaternions are treated as two four-dimensional vectors, the components (Mw, Mx, My, and Mz) of the quaternion product are each given in the form of a sum of products of elements (Aw, Ax, Ay, and Az and Bw, Bx, By, and Bz) of the two four-dimensional vectors. However, the order and signs of the sum of products differ for each component. Hence, when there is a circuit that can perform rearrangement of the elements of the four-dimensional vectors and perform sign inversion simultaneously with product-sum operation, the quaternion product can be expressed by four product-sum operations.
With a 32-bit instruction code, however, the number of bits is not sufficient to represent a vector operation instruction with three operands while including information on rearrangement and sign inversion in an instruction field. Therefore means are often used which realize vector rearrangement and sign inversion by another instruction, store a new vector resulting from the rearrangement and the sign inversion in another register, and then perform operation using the register.
For example, an instruction to perform such vector rearrangement and sign inversion is provided in an instruction set SSE (Streaming SIMD Extensions) for multimedia, which instruction set has been developed by Intel Corporation, an instruction set AltiVec for multimedia, which instruction set has been developed by Motorola Inc., and the like (see Non-Patent Literature, “IA-32 Intel(R) Architecture Software Developer's Manual Volume 1: Basic Architecture,” Intel Corporation, 2004 and Non-Patent Literature, “AltiVec Technology Programming Interface Manual,” Motorola Inc., June 1999)